This application claims priority upon Korean Patent Application No. 2000-14297, filed on Mar. 21, 2000, the contents of which are herein incorporated by reference in their entirety.
The present invention is related to a semiconductor memory device, and, more particular, an input/output sense amplifier circuit that is used in a dynamic random access memory (hereinafter, referred to as xe2x80x9cDRAMxe2x80x9d) device.
A semiconductor memory device, particularly a DRAM device, includes an array of memory cells arranged in a matrix of plural rows and plural columns and circuits for accessing memory cells and transferring data read out from the memory cells to the exterior. As is well known, a transfer path connecting a memory cell to an external region includes a pair of bit lines BLn and BLnB associated with a memory cell MC, a pair of input/output lines IOi and IOiB corresponding to the bit line of the pair, and a pair of data input/output lines DIOj and DIOjB corresponding to the input/output lines of the pair, all of which are illustrated in FIG. 1.
In a concrete way, the input/output line pair IOi and IOiB transfers cell data loaded on the bit line pair to an input/output multiplexer 12 through transistors T1 and T2 (or a column pass gate circuit), which are selected by a column selection line CSL. To the input/output multiplexer 12 (although not shown in the figure) are connected plural input/output line pairs corresponding to the pair of data input/output lines DIOj and DIOjB. That is, one input/output multiplexer 12 connects one of plural pairs of input/output lines with the pair of data input/output lines DIOj and DIOjB, which transfer cell data through the input/output multiplexer 12 to a data input/output sense amplifier circuit 20. Since the size of a bit line sense amplifier 24 is small and input/output line loading and data input/output line loading are very large, an input/output sense amplifier circuit 20 is used to amplify a signal again at an end of the data input/output line pair DIOj and DIOjB.
Generally, an amplifier, which is used for an amplification of input/output signals in a memory device, is classified into a current sense type and a voltage sense type. Considering an operating characteristic, an amplifier of the voltage sense type (hereinafter, referred to as xe2x80x9ca voltage sense amplifierxe2x80x9d) has slower response speed than an amplifier of the current sense type (referred to as xe2x80x9ca current sense amplifierxe2x80x9d). In other words, since the voltage sense amplifier amplifies a signal so as to have a large voltage swing, it takes much time for a signal transition between states. On the other hand, since the current sense amplifier amplifies a signal so as to have a small voltage swing, it takes a short time for a signal transition between states as compared with the voltage sense amplifier.
Continuing to refer to FIG. 1, the input/output sense amplifier circuit 20 consists of a current sense amplifier 14, a voltage sense amplifier 16 and a latch circuit 18. The current sense amplifier 14 having a rapid operation speed amplifies data signals (or differential signals of different levels) on the data input/output lines DIOj and DIOjB, and the voltage sense amplifier 16 again amplifies the data signals CSA and CSAB from the current sense amplifier 14. The latch circuit 18 converts voltage levels of data signals DIF and DIFB from the voltage sense amplifier into CMOS levels, and transfers data signals DOUT and DOUTB of the CMOS levels to an output buffer circuit 22. FIG. 2 is a detailed circuit diagram of the input/output sense amplifier circuit 20 and the output buffer circuit 22.
Referring to FIG. 2, the current sense amplifier 14 and the voltage sense amplifier 16 are activated when a signal xe2x80x9cIOSAExe2x80x9d is at a logic high level. The current sense amplifier 14 consists of two PMOS transistors MP1 and MP2 and three NMOS transistors MN1, MN2 and MN3 connected as illustrated in FIG. 2. Current sense amplifier 14 senses and amplifies signals on the data input/output lines DIOj and DIOjB. The voltage sense amplifier 16 consists of two differential amplifiers, each of which comprises two PMOS transistors and three NMOS transistors connected as illustrated in the figure. The voltage sense amplifier 16 receives data signals CSA and CSAB from the current sense amplifier 14, and amplifies voltage levels of the received data signals CSA and CSAB to output data signals DIF and DIFB having amplified voltage levels. The latch circuit 18 converts the voltage levels of the data signals DIF and DIFB into CMOS levels, using four PMOS transistors MP7, MP8, MP9 and MP10 and three NMOS transistors MN9, MN10 and MN11 connected as illustrated in the figure.
In operation, if the signal IOSAE transits from a logic low level to a logic high level, the current sense amplifier 14 and the voltage sense amplifier 16 of the input/output sense amplifier circuit 20 are simultaneously activated. Data signals transferred to the data input/output lines DIOj and DIOjB are sensed and amplified by the current sense amplifier 14, and the data signal CSA and CSAB thus amplified are transferred to the voltage sense amplifier 16. The voltage sense amplifier 16 amplifies the data signals CSA and CSAB from the current sense amplifier 14. Among data signals DIF and DIFB amplified by the voltage sense amplifier 16, one having a logic high level has a voltage level of about 1.5V. The latch circuit 18 is inactivated when a signal LAT is at a logic low level. At this time, output terminals DOUT and DOUTB thereof are precharged with the same voltage VDD through the PMOS transistors MP9 and MP10. The latch circuit 18 is activated at a logic high level of the signal LAT to latch output signals DIF and DIFB of the voltage sense amplifier 16. At this time, among the output signals DOUT and DOUTB of the latch circuit, one having a logic high level has a CMOS level, i.e. a power supply voltage VDD level.
In the conventional input/output sense amplifier circuit 20, as the signals DOUT and DOUTB from the latch circuit 18 are outputted relatively rapidly, read time of the DRAM device is reduced. That is, the read time (or an access time from column address) tAA thereof is shortened. However, in the case of establishing a low-to-high transition point of time too rapidly, previously outputted data signals (i.e. output signals of the voltage sense amplifier that are outdated) are supplied as input signals of the latch circuit 18. This will be referred to as an invalid sensing operation. As illustrated in FIG. 2, the cross-coupled PMOS transistors MP7 and MP8 of the latch circuit 18 continue to maintain a latched value.
In a case where invalid data are applied to the latch circuit 18, the cross-coupled PMOS transistors MP7 and MP8 latch the invalid data. Since the latched invalid data have to be flipped into currently inputted valid data, much time is taken to output the valid data. In order to secure a stable operation of the latch circuit 18, therefore, there is given a predetermined time margin (refer to FIG. 4, Tmargin) at a low-to-high transition point of time of the signal LAT applied to the latch circuit 18. It means that the read time tAA of the DRAM device is limited by the low-to-high transition point of time (or an activation point of time) of the signal LAT.
It is therefore an object of the invention to provide a semiconductor memory device being capable of reducing read time.
It is another object of the invention to provide an input/output sense amplifier circuit of a semiconductor memory device with a latch circuit, the amplifier circuit having a variable voltage gain. This and other objects, advantages and features of the present invention are provided by a dynamic random access memory device, which comprises at least one pair of bit lines; a pair of input/output (I/O) lines corresponding to the bit lines of the pair; and an I/O sense amplifier circuit coupled to the I/O lines of the pair. The I/O sense amplifier circuit comprises a current sense amplifier for sensing a current differential between the input/output lines to output differential signals; a voltage sense amplifier for amplifying voltages of the differential signals from the current sense amplifier; and a latch circuit for latching the differential signals from the voltage sense amplifier in response to a latch signal, wherein the latch circuit includes a first differential amplifier for receiving the differential signals from the voltage sense amplifier; a second differential amplifier for receiving the differential signals from the voltage sense amplifier; and gain control means coupled between output terminals of the first and second differential amplifiers, the gain control means setting a voltage gain of each of the first and second differential amplifiers that varies in response to the latch signal.
In one embodiment, the gain control means comprises a first resistive element having one end coupled to the output terminal of the first differential amplifier; a second resistive element having one end coupled to the output terminal of the second differential amplifier; and a switch transistor coupled between the other ends of the first and second resistive elements, the switch transistor being switched on and off according to a logic level of the latch signal.